Such interconnects may be employed in semiconductor devices, e.g. integrated circuits (ICs).
In conventional ICs, it is necessary to establish electrical contact between conductive layers that are formed on different levels of metallization and separated by dielectric layers.
An IC interconnect may thus comprise vias and lines for interconnecting different parts of an underlying semiconductor substrate on which components, e.g. transistors, are formed. A line extends in a plane parallel to the plane of the semiconductor substrate. A via extends in a direction perpendicular to the plane of the semiconductor substrate, through a dielectric layer. Both the lines and the vias are formed by depositing electrically conductive material within a stack of patterned dielectric layers.
Improvements in the performance of semiconductor devices (speed, low power consumption) have required a large number of changes of the materials that have been used up till now.
In order to reduce the capacitance that exists between the lines formed in a layer of dielectric material, dielectric materials with a low permittivity coefficient “k”, typically lower than 4.2, or with an ultra-low-k, typically lower than 2.4, may be used. The interline capacitance is indeed proportional to the permittivity coefficient k of the dielectric material that is used. The ULK dielectric materials may comprise porous materials. The porous materials have a relatively low density.
The improvements in the performance have also been achieved through the use of an electrically conductive material that is more conductive than aluminum, which has traditionally been used to make the interconnect lines. Copper, whose resistivity is nearly half that of aluminum doped with copper, has shown itself to be the best candidate.
The use of ULK dielectric materials and copper allow for reduction in the capacitance C that exists between the lines and the resistance R of the interconnect respectively. The value of the propagation constant RC may hence be reduced. A semiconductor device with a propagation constant RC having a relatively low value may thus operate properly at relatively high frequencies; stated otherwise, the new materials allow for improvement in the performance of semiconductor devices.
These new materials may be employed in the well-known Damascene or Dual Damascene processes. To obtain a metallization level n, a dielectric layer made of a first dielectric material is deposited on a layer of level n−1. Trenches are etched within the dielectric layer, the trenches corresponding to portions of the interconnect, e.g. lines and vias. A metallization operation, in which a thin metallic barrier is deposited, is performed and the electrically conductive material is subsequently deposited so as to fill the trenches and polished until it is level with the upper surface of the dielectric layer.
The Damascene or Dual Damascene processes are well suited for producing copper lines and vias because, although copper has advantageous electrical properties for narrow lines, it cannot be etched at ambient temperature. Additionally, the Damascene and Dual Damascene processes may be used with other metals used to form lines and vias.
During the Damascene or Dual Damascene processes, the etching of the trenches may be followed by other patterning operations such as stripping and cleaning. The stripping operation allows for removal of residues of photosensitive resin, and/or the residues of the etch chemistry. Wet cleaning operations may also be performed to remove contaminants.
However, a patterning operation, i.e. etching, stripping and/or cleaning, may damage a portion of the dielectric layer. For example, cleaning solutions used for stripping etch residues may penetrate into the already damaged dielectric layer and provide an additional deterioration of the dielectric layer.
In the case of porous dielectric materials, the dielectric layer may comprise a damaged portion on the walls of the trenches. The damaged portion may have a relatively large width, e.g. 10 or 20 nm.
The permittivity of the damaged portion is higher than the permittivity of the first dielectric material, thus increasing a total permittivity of the etched dielectric layer. For example, the interline permittivity of a deposited dielectric layer may rise from 2.4 to 3.5 after the patterning operations. The interline capacitance being proportional to the overall permittivity, the damaging of the dielectric layer by the patterning operation leads to an increase of the interline capacitance and of the propagation constant RC.
Furthermore, a porous dielectric material may be hydrophilic. If water molecules penetrate into the dielectric layer, the overall permittivity may also increase. The water molecules may also disturb the operation of the semiconductor device.
Furthermore, metal containing precursor molecules used for a vapor deposition of the thin metallic barrier may diffuse into the pores of the porous dielectric layer, which may lead to a short circuit. If the thin metallic barrier has discontinuities, copper atoms or copper ions may also penetrate into the dielectric layer.
There is thus a need for a dielectric layer having a small overall permittivity and in which the pores are protected from diffusion of water or metal molecules.
It is known in the art to provide an intentional densification of the dielectric material on the side walls of the trench. The intentional densification may be performed after the etching, for example using a surface treatment or plasma bombardment.
The densification provides a relative closing of the pores of the damaged portion. The relative closing of such peripheral pores allows avoiding diffusion of water and metal molecules.
However, by locally increasing the dielectric permittivity, the intentional densification also increases the overall permittivity of the dielectric layer. Furthermore, a certain width is required for the damaged portion to protect the pores from diffusion. As the dimensions of the semiconductor devices shrink, the ratio between the volume of the damaged portion and the global volume of the etched dielectric layer increases, thus increasing the global permittivity of the dielectric layer and increasing the propagation constant RC.
It is also known in the art to deposit a capping layer on the etched dielectric layer to protect the pores of the dielectric layer from diffusion. See, “O2-Plasma Degradation of Low-K Organic Dielectric and its Effective Solution for Damascene Trenches”, Ching-Fa Yeh et al., 2000 5th International Symposium on Plasma Process-Induced Damage, which describes such a capping operation.
The capping layer may be made of a dielectric material having a relatively higher permittivity and a relatively higher density than the porous dielectric material of the dielectric layer. Hence, the capping layer allows to shield the pores from diffusion of water molecules or metal containing molecules, e.g. tantalum containing vapor used in atomic layer deposition (ALD) or chemical vapor deposition (CVD). The thin metallic barrier may subsequently be deposited on the capping layer without metallic deposition inside the porous dielectric material.
However, the depositing of the capping layer reduces the volume to be filled with copper, which may cause problems in filling the trenches with copper. Furthermore, the resistivity of the interconnect may increase when the section of the interconnect becomes in the order of the mean free path of the electron. As the dimensions of the semiconductor devices shrink, the capping leads inevitably to an increase of the resistance of the interconnect, and thus to an increase of the value of the propagation constant RC.
As a consequence, there is still a need for a semiconductor device comprising an interconnect made of an electrically conductive material in a dielectric layer and having a relatively low propagation constant value RC.